5CSXFC6C6U23C6N - Cyclone V SX SoC FPGA, 110K LE, 925MHz | Intel
MPN: 5CSXFC6C6U23C6N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $412 | $412.00 |
| 10 | $388.5 | $3,885.00 |
| 100 | $355 | $35,500.00 |
| 500 | $318.75 | $159,375.00 |
| 1,000 | $285 | $285,000.00 |
Drop-in alternatives for 5CSXFC6C6U23C6N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →5CSXFC6C6U23C6N Maximum Ratings & Electrical Characteristics
| Series | Cyclone V SX SoC FPGA |
| Family | Cyclone V SX |
| Logic Elements | 110,000 |
| Processor Core | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Fabric Frequency | 925 MHz |
| Process Technology | 28 nm low-power |
| Core Supply Voltage | 1.1 V |
| Package | 672-UBGA (UFBGA) 23x23 mm |
| Mounting Type | Surface Mount (BGA) |
| Operating Temperature | 0 C to +85 C (commercial) |
| Number of I/O | 145 (per JAK Electronics comparison) |
| Embedded Memory | approximately 4,160 Kbits |
| DSP Blocks | approximately 112 |
| RoHS Status | Compliant |
| MSL Level | 3 (per typical BGA handling) |
5CSXFC6C6U23C6N 672-ubga (ufbga) 23x23 mm Pin Configuration Guide
Complete pinout information for 5CSXFC6C6U23C6N (672-ubga (ufbga) 23x23 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 5CSXFC6C6U23C6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5CSXFC6C6U23C6N is suitable for 6 applications: Industrial Machine Vision, Motor Control and Industrial Drives, Software Defined Radio Front End, Factory Automation Controllers, Broadcast Video Processing, Automotive ADAS Prototyping.
Industrial Machine Vision
The 5CSXFC6C6U23C6N fits industrial machine vision because the Dual ARM Cortex-A9 HPS runs the vision stack (OpenCV, Linux, image acquisition) while the 110K LE FPGA fabric implements parallel pixel pipelines, Bayer demosaicing, and object detection at line rate. The integrated HPS-FPGA AXI bridges deliver 128-bit data paths between the ARM cores and custom datapath, eliminating external processor-to-FPGA interconnect. The 672-UBGA package exposes sufficient GPIO and high-speed transceiver lanes to drive dual Camera Link or MIPI CSI-2 cameras simultaneously. Industrial temperature operation and the 28 nm low-power process suit 24/7 factory deployments.
Recommended
Motor Control and Industrial Drives
The 5CSXFC6C6U23C6N is well matched to industrial motor control because the FPGA fabric executes field-oriented control (FOC), PWM generation, and encoder feedback at sub-microsecond latency, while the ARM Cortex-A9 HPS runs the higher-level motion profiler and EtherCAT/MODBUS stack. The approximately 112 DSP blocks provide ample multiply-accumulate throughput for the current-loop math, and the on-chip DDR3 controller streams parameter tables without external memory contention. The wide 145-I/O budget in UFBGA-672 supports three-phase inverter feedback and resolver excitation simultaneously.
Recommended
Software Defined Radio Front End
The 5CSXFC6C6U23C6N supports software defined radio front ends because the FPGA fabric implements DDC/DUC, channelization filters, and digital predistortion at baseband sample rates, offloading the ARM Cortex-A9 HPS to handle network protocols and control plane. The Cyclone V SX fabric runs approximately 925 MHz internal performance, suitable for LTE and tactical radio baseband. Hard transceivers on the device family provide the SerDes lanes needed for ADC/DAC interfacing, while the HPS runs Linux for waveform configuration. Lower static power than Arria/Cyclone 10 GX parts makes it attractive for portable SDR.
Recommended
Factory Automation Controllers
The 5CSXFC6C6U23C6N suits factory automation controllers because the dual ARM Cortex-A9 MPCore runs a deterministic RTOS or LinuxCNC for PLC logic and HMI, while the FPGA fabric implements deterministic EtherCAT, PROFINET, or EtherNet/IP slave nodes with hardware-cycle timing. The hard Ethernet MACs in the HPS simplify integration with industrial Ethernet stacks, and the abundant GPIO through the 672-UBGA package supports parallel field-bus signaling. The 28 nm low-power process reduces thermal load in sealed control cabinets, and the 110K LEs provide headroom for custom protocol extensions.
Recommended
Broadcast Video Processing
The 5CSXFC6C6U23C6N handles broadcast video processing because the FPGA fabric implements SDI/HDMI bridging, color space conversion, and audio embedding at full 1080p60 rates without CPU intervention, while the ARM HPS handles control plane and metadata insertion. The DDR3 hard controller streams uncompressed video frames between FPGA logic and ARM memory, and the 4,160 Kbits embedded RAM provides line buffers for cross-conversion. The wide UFBGA-672 footprint exposes sufficient high-speed LVDS pairs for multi-channel SDI at 3 Gbps.
Recommended
Automotive ADAS Prototyping
The 5CSXFC6C6U23C6N enables automotive ADAS prototyping because the dual ARM Cortex-A9 HPS runs sensor fusion and obstacle classification algorithms while the FPGA fabric implements low-latency radar FFT, lidar point-cloud clustering, and camera pre-processing. The Cyclone V SX architecture supports multiple sensor data streams in parallel, and the HPS-FPGA AXI fabric provides deterministic latency for safety-critical paths. Note that for production automotive designs, the Cyclone V automotive grade variant (typically designated by an A-speed grade or specific ordering code) is recommended over the commercial 5CSXFC6C6U23C6N.
Recommended
Recommended Products Summary
Engineering reference data for 5CSXFC6C6U23C6N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5CSXFC6C6U23A7N | 5CSXFC6C6U23C7N | 5CSXFC6C6U23C8N | 5CSXFC5C6U23C6N | 5CSXFC4C6U23C6N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-UBGA (UFBGA) 23x23 mm | 672-UBGA (UFBGA) 23x23 mm - same | 672-UBGA (UFBGA) 23x23 mm - same | 672-UBGA (UFBGA) 23x23 mm - same | 672-UBGA (UFBGA) 23x23 mm - same | 672-UBGA (UFBGA) 23x23 mm - same |
| Family | Cyclone V SX | Cyclone V SX | Cyclone V SX | Cyclone V SX | Cyclone V SX | Cyclone V SX |
| Logic Elements | 110,000 | 110,000 | 110,000 | 110,000 | 85,000 (-23%) | 49,000 (-55%) |
| Processor Core | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Speed/Temperature Grade | C6 (commercial) | A7 (automotive/industrial) | C7 (commercial, faster) | C8 (commercial, fastest) | C6 (commercial) | C6 (commercial) |
| Maximum Fabric Frequency | 925 MHz | 925 MHz | 925 MHz | 925 MHz | 925 MHz | 925 MHz |
| Typical Unit Price (qty 1) | approximately 412 USD | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | lower (fewer LEs) | lowest (smallest die) |
Key Differentiators
- Highest density SX SoC option at the C6 speed grade in the same UFBGA-672 footprint (vs 5CSXFC5C6U23C6N)
- Industrial/automotive temperature drop-in available in identical footprint (vs 5CSXFC6C6U23A7N)
- Cyclone V SX sub-family provides higher DSP count than SE alternatives (vs 5CSEBA6U23I7N)
Design Notes
The 672-UBGA 23x23 mm package uses a 1.0 mm ball pitch, which requires microvia or via-in-pad PCB technology for reliable breakout. Use at least a 4-2-4 stacked-via construction with 0.4 mm laser-drilled microvias, and ensure the BGA land pads meet IPC-7095 nominal-diameter specifications. Plan for at least 6 PCB layers to route out 145 user I/O plus DDR3, transceivers, and clock signals without excessive via stubs. Decoupling must follow the Intel Cyclone V pin connection guidelines with bulk 220 uF polymer caps near each GPIO bank supply pin.
Estimated: at heavy DSP utilization consuming the full 110K LE fabric at approximately 85% toggle rate with all 112 DSP blocks active, the 5CSXFC6C6U23C6N dissipates approximately 3-5 W. With the UFBGA-672 theta-JA typically around 15-20 C/W on a JEDEC JESD51 4-layer test board, junction temperature rises 45-100 C above ambient. For closed-enclosure industrial designs, evaluate thermal performance in-system with thermocouples on the package top. Consider attaching a heatsink or thermal pad to the package top side if ambient temperature exceeds 60 C.
Three common pitfalls when designing with the 5CSXFC6C6U23C6N: (1) Forgetting to instantiate the HPS first-stage bootloader (preloader) before Linux boots - the HPS cannot boot without valid preloader code in QSPI or SD card. (2) Mixing 1.1 V core and 1.2 V transceiver supplies without proper sequencing - the Cyclone V datasheet mandates power-on sequence with the HPS core rail stable before FPGA fabric enters user mode. (3) Routing DDR3 signals without matching the 50 ohm impedance and length-matching per the Cyclone V external memory interface guidelines - failures here are notoriously hard to debug post-tapeout.
Compliance Information
RoHS compliance per DigiKey product listing. C6 grade is commercial temperature; for AEC-Q100 automotive applications, choose the automotive-grade ordering variant or 5CSXFC6C6U23A7N for extended industrial/automotive temperature.
