IQEH46NE2LM7UCGSCATMA1 - 25V 440A OptiMOS 7 N-FET | Infineon
MPN: IQEH46NE2LM7UCGSCATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.85 | $2.85 |
| 10 | $2.58 | $25.80 |
| 100 | $2.21 | $221.00 |
| 500 | $1.92 | $960.00 |
| 1,000 | $1.65 | $1,650.00 |
IQEH46NE2LM7UCGSCATMA1 Overview
An N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal switch used to efficiently route and switch high currents in power conversion systems. Belonging to the MOSFET -> power MOSFET -> discrete semiconductor hierarchy, OptiMOS 7 represents Infineon's latest generation of low-voltage (typically <60 V) trench MOSFETs optimized for both hard- and soft-switching topologies including buck, buck-boost, and totem-pole PFC. The Source-Down packaging places the source connection on the bottom of the die, improving thermal performance and enabling top-side cooling.
Key features include a 25 V drain-source breakdown rating, 0.46 mOhm max RDS(on), an operating temperature range suitable for industrial and compute applications, and an integrated source-down thermal pad. The PG-WHTFN-9-1 package provides a compact footprint optimized for high-density power designs in AI servers and data center power supplies, where every square millimeter of PCB real estate and every milliohm of conduction loss translates directly into system efficiency.
From an architecture standpoint, the OptiMOS 7 process uses an advanced trench cell structure with epitaxial refinement that minimizes both on-state conduction losses (low RDS(on)) and switching losses (low Qg, low Qrr). This balance is critical for high-frequency SMPS designs where traditional MOSFETs compromise between conduction and switching performance. The Source-Down package topology further reduces package resistance and inductance by relocating the source bond wires to a direct PCB connection.
Typical applications include AI server and data center 48V-to-Point-of-Load (PoL) conversion, telecom brick DC-DC converters, USB-PD and high-power USB Type-C chargers, graphics card and accelerator (GPU/ASIC) power stages, and high-frequency synchronous rectification. The low RDS(on) and small footprint make it particularly suited for AI computing platforms where multiple parallel MOSFETs are stacked to deliver hundreds of amps at low voltage.
Design consideration: at 25 V VDS with potentially high di/dt transients, PCB layout must minimize source-loop inductance to control ringing and EMI. Place the gate driver within 5 mm of the gate pin and use a 1 Ohm gate-source resistor for damping. Ensure adequate copper pour on the source-down thermal pad - typically 1 oz copper minimum with thermal vias to inner planes for heat extraction.
This page synthesizes Infineon OptiMOS 7 family specifications, drop-in Source-Down package alternatives, distributor stock signals, and practical design notes for AI server power applications not found in the manufacturer datasheet alone.
Drop-in alternatives for IQEH46NE2LM7UCGSCATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IQEH46NE2LM7UCGSCATMA1 (same form factor and footprint) — differing in Package, Operating Temperature Range, Technology, RoHS Status, Continuous Drain Current (ID) at Ta.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IQEH54NE2LM7UCGATMA1
✅ Drop-In✓ In Stock
$1.95 / Unit
View Datasheet →IQEH68NE2LM7UCGATMA1
✅ Drop-In✓ In Stock
$1.35 / Unit
View Datasheet →IQEH50NE2LM7ZCGATMA1
✅ Drop-In✓ In Stock
$1.42 / Unit
View Datasheet →IQDH35N03LM5SCATMA1
✅ Drop-In✓ In Stock
$2.05 / Unit
View Datasheet →IQDH88N06LM5CGSCATMA1
✅ Drop-In✓ In Stock
$2.31 / Unit
View Datasheet →IQEH46NE2LM7UCGSCATMA1 Maximum Ratings & Electrical Characteristics
| Transistor Type | N-Channel MOSFET |
| Technology | OptiMOS 7 (trench) |
| Drain-Source Voltage (VDS) | 25 V |
| Continuous Drain Current (ID) at TC | 440 A |
| Continuous Drain Current (ID) at TA | 57 A |
| Power Dissipation at TA | 2.5 W |
| Power Dissipation at TC | 150 W |
| Maximum On-Resistance (RDS(on)) | 0.46 mOhm |
| Gate Threshold Voltage (VGS(th)) | 2 V |
| Package | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) |
| Mounting Type | Surface Mount |
| Polarity / Channel Type | Single N-Channel |
| Operating Mode | Enhancement-mode |
| Topology Suitability | Hard- and soft-switching |
| RoHS Status | Compliant |
IQEH46NE2LM7UCGSCATMA1 Pin Configuration
| Pin 1 | Gate — Gate input - drives the MOSFET channel on/off |
| Pin 2 | Source — Source connection (also thermal pad on bottom) |
| Pin 3 | Source — Source connection (also thermal pad on bottom) |
| Pin 4 | Source — Source connection (also thermal pad on bottom) |
| Pin 5 | Drain — Drain connection |
| Pin 6 | Drain — Drain connection |
| Pin 7 | Drain — Drain connection |
| Pin 8 | Drain — Drain connection |
| Pin 9 | Drain — Drain connection |
Safe Operating Area (DC)
Typical Applications
IQEH46NE2LM7UCGSCATMA1 is suitable for 6 applications: AI Server 48V-to-Point-of-Load Conversion, GPU / Accelerator Card Power Stages, USB-PD 3.1 High-Power Chargers (140W-240W), Telecom Brick DC-DC Converters, High-Frequency Synchronous Rectification, Industrial Robotics and Automation Power.
AI Server 48V-to-Point-of-Load Conversion
The IQEH46NE2LM7UCGSCATMA1 fits AI server 48V-to-PoL conversion because its 440 A TC continuous current rating and 0.46 mOhm maximum RDS(on) directly support paralleled synchronous rectifier stages delivering hundreds of amps at 12 V or 5 V to GPUs and AI accelerators. Placed as the low-side FET in a buck or buck-boost stage, it drops less than 90 mW per ampere of conduction loss, helping meet 80+ Titanium and Open Compute Project efficiency targets. The 3.3x3.3 mm Source-Down PQFN footprint allows 6-8 devices to be paralleled under a single GPU socket without exceeding the CPU VR area budget. Estimated: at 200 A conduction per device with 4 paralleled FETs (800 A total), total conduction loss is ~74 W per phase, well within the 150 W TC rating of each device.
Recommended
GPU / Accelerator Card Power Stages
The IQEH46NE2LM7UCGSCATMA1 fits GPU and AI accelerator card power stages because its 25 V VDS and 440 A TC rating make it ideal for the 12 V input rail common on PCIe Gen5/Gen6 add-in cards. With 0.46 mOhm RDS(on) and the 3.3x3.3 mm Source-Down footprint, designers can parallel 4-6 devices per phase to deliver 500-800 A peak transient current demanded by GPU compute bursts. The Source-Down topology pulls heat directly into the PCB copper, allowing the GPU heatsink airflow to extract waste heat without dedicated MOSFET cooling. Estimated: at 300 A burst current across 4 paralleled FETs (75 A each), per-device conduction loss is ~2.6 W at peak, easily handled by standard PCB thermal design.
Recommended
USB-PD 3.1 High-Power Chargers (140W-240W)
The IQEH46NE2LM7UCGSCATMA1 fits USB-PD 3.1 high-power charger applications because its 25 V VDS comfortably exceeds the 28 V USB-PD extended-power-range (EPR) bus voltage with adequate derating margin. With 0.46 mOhm RDS(on) and 440 A TC rating, a single device can handle the synchronous rectification stage of a 240 W charger at full load without paralleling. The 3.3x3.3 mm Source-Down PQFN footprint keeps the charger PCB compact enough for laptop and travel-charger form factors. Compared to older 40 V or 60 V MOSFETs, the 25 V rating trades higher VDS margin for substantially lower RDS(on), boosting efficiency by 1-2% at the typical 20 V USB-PD output voltage.
Recommended
Telecom Brick DC-DC Converters
The IQEH46NE2LM7UCGSCATMA1 fits telecom brick DC-DC converters because its 25 V VDS rating aligns with the 48V telecom bus stepped down to 12 V or 5 V via isolated brick converters. The 0.46 mOhm RDS(on) and 440 A TC rating enable high-efficiency (>96%) conversion at full brick load (typically 600-1200 W), meeting NEBS and ETSI telecom efficiency requirements. The Source-Down PQFN 3.3x3.3 package allows high-density layout on the brick's secondary-side synchronous rectifier bridge. Compared to planar-can MOSFETs of similar rating, the Source-Down package cuts PCB area by ~40% and reduces thermal resistance by ~30%, enabling smaller and cooler-running bricks.
Recommended
High-Frequency Synchronous Rectification
The IQEH46NE2LM7UCGSCATMA1 fits high-frequency synchronous rectification because its OptiMOS 7 trench process minimizes body-diode reverse-recovery charge (Qrr) and output capacitance (Coss), reducing switching losses at 500 kHz to 1 MHz operating frequencies. The 0.46 mOhm RDS(on) and 440 A TC rating allow direct replacement of larger planar MOSFETs in LLC and phase-shift full-bridge topologies. The Source-Down package's low parasitic inductance reduces voltage overshoot during hard commutation, enabling simpler snubber design. Estimated: at 500 kHz switching frequency with 200 A RMS, total switching loss per cycle is ~5-8 uJ per device, versus ~15-20 uJ for legacy 40 V MOSFETs of similar RDS(on).
Recommended
Industrial Robotics and Automation Power
The IQEH46NE2LM7UCGSCATMA1 fits industrial robotics and automation power stages because its 25 V VDS rating covers 24 V industrial bus rails and 12 V motor-drive intermediate rails with margin. The 440 A TC rating and 0.46 mOhm RDS(on) make it suitable for high-current motor-drive synchronous rectification, where traditional planar MOSFETs would require 2-3 paralleled devices to match performance. The Source-Down PQFN 3.3x3.3 package and 150 W TC power dissipation enable compact motor-drive PCB layouts inside robot joint enclosures. Compared to IGBTs in this current range, the OptiMOS 7 MOSFET switches 5-10x faster, enabling higher PWM frequencies and quieter motor operation.
Recommended
Recommended Products Summary
Engineering reference data for IQEH46NE2LM7UCGSCATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IQEH54NE2LM7UCGATMA1 | IQEH68NE2LM7UCGATMA1 | IQEH50NE2LM7ZCGATMA1 | IQDH35N03LM5SCATMA1 | IQDH88N06LM5CGSCATMA1 |
|---|---|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) - same | PG-WHTFN-9-1 (PQFN 3.3x3.3 Source-Down) - same |
| Technology Generation | OptiMOS 7 | OptiMOS 7 | OptiMOS 7 | OptiMOS 7 | OptiMOS 5 | OptiMOS 5 |
| Topology Suitability | Hard- and soft-switching | Hard- and soft-switching | Hard- and soft-switching | Hard- and soft-switching | Hard- and soft-switching | Hard- and soft-switching |
Key Differentiators
- Lowest RDS(on) in 25 V OptiMOS 7 Source-Down family at 0.46 mOhm max (vs IQDH35N03LM5SCATMA1)
- 25 V VDS optimized for 12 V/5 V PoL - lowest conduction loss in its voltage class (vs IQEH54NE2LM7UCGATMA1)
- Source-Down PQFN 3.3x3.3 package with bottom-side source for direct PCB cooling (vs IQDH88N06LM5CGSCATMA1)
Design Notes
Estimated: at 440 A continuous conduction with 25 mOhm effective on-resistance (including package), power dissipation per device is ~4.84 kW which would far exceed the 150 W TC rating. In practice the MOSFET is pulsed (10-50% duty cycle) in switching applications. The Source-Down package routes heat directly into PCB copper; use at least 6 thermal vias (0.3 mm drill, 1 oz copper plating) under the source pad to inner ground planes. A 2 oz copper outer layer on a 4-layer FR4 board keeps junction-to-ambient thermal resistance around 30-40 C/W, allowing ~4 W continuous dissipation at TA=25 C with no airflow.
Place the gate driver within 5 mm of the gate pin to minimize gate-loop inductance. Use a 1-10 Ohm gate resistor for switching speed / EMI tuning and a 10 kOhm pull-down resistor from gate to source to prevent spurious turn-on during power-up. The Source-Down package places the source pad on the bottom - connect this pad directly to a ground copper pour with at least 4 thermal vias for heat extraction. Keep source-loop inductance (drain-switch-source) below 2 nH by minimizing the loop area between the FET, the high-side switch, and the input capacitor.
Do not exceed 25 V drain-source voltage even for transient spikes - the OptiMOS 7 process has tight avalanche margin compared to older generations. Ensure the gate-source voltage never exceeds +/-20 V absolute maximum; use a gate driver with split supplies (e.g., +10 V / -2 V) for hard-switching applications to prevent Miller-induced turn-on. Never operate the device in linear mode (high VDS at high ID simultaneously) for more than a few milliseconds - the SOA is conservative in this region. Verify the body diode reverse-recovery behavior before using in synchronous rectification at >500 kHz.
Route the gate trace on an inner layer with ground shielding on both sides to prevent coupling from the switching node. Use a kelvin source connection (separate source-sense trace back to the gate driver ground) to eliminate source-inductance feedback that would otherwise slow switching and increase switching loss. For paralleled FET configurations, place gate resistors individually per device (not shared) to prevent parasitic oscillation. Symmetric layout of paralleled devices is essential for current sharing; aim for <2 mm positional tolerance between paralleled FETs.
Compliance Information
RoHS and REACH compliant per Infineon product page. Halogen-free per Infineon OptiMOS 7 datasheet. Conflict-minerals compliant per Infineon supplier declarations.
