10AX090N2F45E2LG - Arria 10 GX FPGA, 900K LE, 1932-FCBGA | Intel
MPN: 10AX090N2F45E2LG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7619.06 | $7,619.06 |
| 10 | $7238.11 | $72,381.10 |
| 100 | $6857.16 | $685,716.00 |
| 500 | $6476.2 | $3,238,100.00 |
| 1,000 | $6095.25 | $6,095,250.00 |
Drop-in alternatives for 10AX090N2F45E2LG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AX090N2F45E2SG
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$4943.22 / Unit
View Datasheet β10AX090N2F45E1SG
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$10250 / Unit
View Datasheet β10AX090N2F45E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory (bits) | 59,234,304 |
| User I/O Pins | 768 |
| Core Voltage | 0.9 V |
| Process Technology | 20 nm |
| Package | 1932-ball FCBGA (FBGA) |
| Package Type | Flip-Chip BGA, surface mount |
| Operating Temperature Grade | Enhanced (E2) |
| Lead-Free / RoHS | Yes (per part suffix LG) |
| Configuration Memory | SRAM-based, volatile (external flash required) |
| Mounting Type | Surface Mount |
| Lifecycle Status | Active |
10AX090N2F45E2LG Pin Configuration
| Pin Bank 3A | User I/O Bank 3A β General-purpose user I/O and high-speed differential pairs |
| Pin Bank 3B | User I/O Bank 3B β General-purpose user I/O |
| Pin Bank 3C | User I/O Bank 3C β General-purpose user I/O |
| Pin Bank 4A | User I/O Bank 4A β General-purpose user I/O |
| Pin Bank 4B | User I/O Bank 4B β General-purpose user I/O |
| Pin Bank 4C | User I/O Bank 4C β General-purpose user I/O |
| Pin Bank 5A | User I/O Bank 5A β High-voltage I/O bank |
| Pin Bank 5B | User I/O Bank 5B β High-voltage I/O bank |
| Pin Bank 6A | User I/O Bank 6A β High-voltage I/O bank |
| Pin Bank 6B | User I/O Bank 6B β High-voltage I/O bank |
| Pin Bank 7A | User I/O Bank 7A β High-voltage I/O bank |
| Pin Bank 7B | User I/O Bank 7B β High-voltage I/O bank |
| Pin Bank 7C | User I/O Bank 7C β High-voltage I/O bank |
| Pin Bank 8A | User I/O Bank 8A β High-voltage I/O bank |
| Pin Bank 8B | User I/O Bank 8B β High-voltage I/O bank |
| Pin Bank 9A | User I/O Bank 9A β High-voltage I/O bank |
| Pin Bank L0 | Transceiver Bank L0 β High-speed serial transceiver lanes |
| Pin Bank L1 | Transceiver Bank L1 β High-speed serial transceiver lanes |
| Pin Bank L2 | Transceiver Bank L2 β High-speed serial transceiver lanes |
| Pin Bank L3 | Transceiver Bank L3 β High-speed serial transceiver lanes |
| Pin Bank R0 | Transceiver Bank R0 β High-speed serial transceiver lanes |
| Pin Bank R1 | Transceiver Bank R1 β High-speed serial transceiver lanes |
| Pin Bank R2 | Transceiver Bank R2 β High-speed serial transceiver lanes |
| Pin Bank R3 | Transceiver Bank R3 β High-speed serial transceiver lanes |
| Pin VCC | Core / Aux / I/O Power β 0.9 V core and auxiliary supplies plus I/O bank supplies (multiple pins) |
| Pin GND | Ground β Common ground reference (multiple pins) |
| Pin NC | No-Connect / Reserved β Unused balls per package pinout (multiple pins) |
| Pin JTAG_TCK | JTAG TCK β JTAG test clock |
| Pin JTAG_TMS | JTAG TMS β JTAG test mode select |
| Pin JTAG_TDI | JTAG TDI β JTAG test data in |
| Pin JTAG_TDO | JTAG TDO β JTAG test data out |
| Pin CONFIG_DONE | Configuration Done β Open-drain configuration complete indicator |
| Pin nCONFIG | nCONFIG β Configuration start / reset (active low) |
| Pin nSTATUS | nSTATUS β Configuration status (active low) |
| Pin CLK_USR | Dedicated Clock Inputs β Differential clock input pins (multiple) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090N2F45E2LG is suitable for 6 applications: 4K/8K Video Broadcast Infrastructure, Wireless Baseband and DSP Acceleration, Radar and Signal Intelligence (SIGINT), High-Performance Computing (HPC) Acceleration, Industrial Test and Measurement Instrumentation, Medical Imaging and Diagnostic Equipment.
4K/8K Video Broadcast Infrastructure
The 10AX090N2F45E2LG's 900K logic elements and 59 Mb embedded memory make it a strong fit for 4K and 8K video broadcast pipelines, including multi-channel SDI ingest, frame-rate conversion, and HDR tone mapping. The device handles 12G-SDI quad-link aggregation at production frame rates when paired with Intel's video IP cores and external DDR4 memory. Compared with smaller Arria 10 devices, the 900K fabric absorbs multiple parallel video processing paths without dropping frames, and the 1932-ball FCBGA exposes the transceiver lanes required for SDI, HDMI, and DisplayPort aggregation. Power-sensitive broadcast racks benefit from the 20 nm process's improved performance-per-watt versus older 28 nm Arria V / Stratix V parts.
Recommended
Wireless Baseband and DSP Acceleration
The 10AX090N2F45E2LG is well matched to wireless baseband processing such as LTE, 5G NR PHY layer acceleration, and digital predistortion (DPD) for RF power amplifiers. The 900K LE and abundant DSP blocks run multi-antenna MIMO processing, FFT/IFFT engines, and crest-factor reduction in parallel. The integrated high-speed transceivers interface directly to RF ADC/DAC JESD204B/C links, eliminating companion FPGA glue logic. Compared with a Stratix 10 part, the Arria 10 GX balances cost and thermal envelope for macro-cell base stations and small-cell deployments where thousands of units ship per month.
Recommended
Radar and Signal Intelligence (SIGINT)
Military radar front-end and electronic-warfare systems benefit from the 10AX090N2F45E2LG's combination of high logic density, large embedded memory, and fast transceivers. Pulse compression, beamforming, and direction-finding algorithms run in real time across the 900K fabric, while 59 Mb of block RAM buffers multi-channel ADC samples at gigasample-per-second rates. The 1932-ball FCBGA exposes dedicated transceiver pins for direct ADC/DAC connectivity, and the 20 nm Arria 10 process provides radiation-tolerant behavior for high-altitude or space applications when paired with mitigation flows in Quartus Prime.
Recommended
High-Performance Computing (HPC) Acceleration
The 10AX090N2F45E2LG serves as an HPC compute accelerator in data-center and lab-instrument workloads, offloading compute kernels from host CPUs via PCI Express Gen3 links. The 900K fabric runs custom OpenCL or RTL accelerators for genomics, financial Monte Carlo, and machine-learning inference. The 1932-ball FCBGA exposes multiple PCIe hard IP blocks, and the 59 Mb block RAM keeps working sets close to the fabric to minimize external DRAM round-trips. Compared with a Stratix 10 accelerator, this Arria 10 part offers a more attractive cost-per-FLOP for sustained-throughput workloads.
Recommended
Industrial Test and Measurement Instrumentation
High-end oscilloscopes, protocol analyzers, and automated test equipment leverage the 10AX090N2F45E2LG for real-time signal processing, deep acquisition memory, and high-speed serial trigger logic. The 900K LE fabric parallelizes FFT computation, eye-diagram analysis, and protocol decoding across multiple lanes simultaneously. The 1932-ball FCBGA connects directly to high-speed ADC/DAC converters via the device's transceivers, while 768 user I/Os fan out to front-panel connectors, displays, and trigger logic. Compared with smaller Arria 10 devices, the 900K LE budget enables longer acquisition windows and more complex triggering without external pre-processors.
Recommended
Medical Imaging and Diagnostic Equipment
Ultrasound, CT, and MRI image-processing pipelines benefit from the 10AX090N2F45E2LG's real-time DSP throughput and large embedded memory budget. The 900K LE fabric runs beamformers for ultrasound probes, image reconstruction for CT, and gradient processing for MRI in a single device. The 59 Mb of block RAM holds raw channel data, while the transceivers connect to high-channel-count ADC modules. Compared with lower-density Arria 10 parts, the 900K fabric supports higher probe counts and higher frame rates without dropping samples, which is critical for diagnostic-grade image quality.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090N2F45E2LG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090N2F45E2SG | 10AX090N2F45E1SG | 10AX090N2F40I2LG | 10AX090N2F40I1SG | 10AX066N2F40E1SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1932-ball FCBGA | 1932-ball FCBGA (same) | 1932-ball FCBGA (same) | 1517-ball FCBGA (NOT pin-compatible) | 1517-ball FCBGA (NOT pin-compatible) | 1517-ball FCBGA (NOT pin-compatible) |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 660,000 |
| Embedded Memory | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | 59,234,304 bits | [DATA_NEEDED: memory bits for 660K variant] |
| User I/O | 768 | 768 | 768 | [DATA_NEEDED: I/O count for F40] | [DATA_NEEDED: I/O count for F40] | [DATA_NEEDED: I/O count for 660K] |
| Temperature Grade | Enhanced (E2) | Enhanced (E2) | Industrial (E1) | Industrial (I2) | Industrial (I1) | Enhanced (E1) |
| Packaging Media | Tray (LG) | Tape and Reel (SG) | Tape and Reel (SG) | Tray (LG) | Tape and Reel (SG) | Tape and Reel (SG) |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
Key Differentiators
- Highest-density Arria 10 with 900K LE and 59 Mb memory in the F45 footprint (vs 10AX066N2F40E1SG)
- 1932-ball FCBGA with maximum I/O count and transceiver fan-out (vs 10AX090N2F40I2LG (1517-ball))
- Enhanced (E2) temperature grade suitable for thermally stressed deployments (vs 10AX090N2F45E1SG (E1 grade))
Design Notes
Estimated: the 1932-ball FCBGA requires a high-layer-count PCB (typically 14+ layers) with microvia and via-in-pad technology. Route all high-speed transceiver lanes with controlled differential impedance (typically 100 ohm). Provide adequate thermal vias under the package to dissipate the 20 nm Arria 10 power budget. The Intel Arria 10 PCB Design Guidelines provide ball-map and stack-up reference for this package.
Estimated: at typical Arria 10 GX utilization (60-70% LE, mid transceiver activity), the 10AX090N2F45E2LG draws 20-35 W. Use a multi-rail power solution with 0.9 V core, 1.1 V auxiliary, and per-bank I/O supplies. Decoupling must follow Intel's reference capacitor network, with bulk capacitors close to each supply pin. Use a PMBus-compliant point-of-load regulator for telemetry.
Do not substitute the F45 package variant with the F40 package variant on the same PCB layout - the F40 uses a smaller 1517-ball FCBGA. Verify the exact MPN suffix matches your PCB footprint before ordering production units. Confirm operating temperature grade (E1 vs E2 vs I1 vs I2) matches the deployment environment, since under-specifying temperature grade is a common source of field failures.
Place the configuration flash within 4 inches of the MSEL pins to minimize signal integrity issues during FPGA boot. Keep JTAG chain signals away from switching power supplies and high-speed transceivers. For multi-FPGA boards, isolate each FPGA's power and ground planes to prevent return-current coupling. The Arria 10 transceiver signal-integrity checklist (AN 678) provides lane-by-lane routing guidance.
Compliance Information
RoHS / lead-free indicated by the LG suffix. AEC-Q100 not applicable (FPGAs are not qualified automotive ICs in the same sense as discrete power devices). Conflict-minerals compliance follows Intel's standard CMRT declarations.
