5CSXFC6C6U23I7N - Cyclone V SX SoC FPGA, 110K LE, 672-UBGA | Intel
MPN: 5CSXFC6C6U23I7N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $480 | $480.00 |
| 10 | $455 | $4,550.00 |
| 100 | $425 | $42,500.00 |
| 500 | $395 | $197,500.00 |
| 1,000 | $365 | $365,000.00 |
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View Datasheet →5CSXFC6C6U23I7N Maximum Ratings & Electrical Characteristics
| Family | Cyclone V SX |
| Device Variant | 5CSXFC6C6 (logic density code C6, speed grade 6) |
| Logic Elements | 110,000 |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 800 MHz |
| Process Technology | 28 nm TSMC low-power |
| Core Voltage (VCCINT) | 1.1 V |
| Package | 672-pin UBG-A (UBGA), 23 x 23 mm, 1.0 mm ball pitch |
| Operating Temperature | -40C to +100C (Industrial, I7 grade) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| FPGA Fabric Architecture | Logic elements, M10K memory blocks, variable-precision DSP blocks |
| HPS Peripherals | EMAC, USB 2.0, CAN, SPI, I2C, UART, NAND/NOR flash controller, DDR3 controller with ECC |
5CSXFC6C6U23I7N 672-pin ubg-a (ubga), 23 x 23 mm, 1.0 mm ball pitch Pin Configuration Guide
Complete pinout information for 5CSXFC6C6U23I7N (672-pin ubg-a (ubga), 23 x 23 mm, 1.0 mm ball pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 5CSXFC6C6U23I7N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5CSXFC6C6U23I7N is suitable for 7 applications: Industrial Motor Control, Video Surveillance and Machine Vision, Automotive Infotainment Head Unit, Industrial Ethernet Protocol Bridge, Edge AI Inference Gateway, Medical Diagnostic Imaging, Aerospace Avionics Subsystem.
Industrial Motor Control
The 5CSXFC6C6U23I7N fits industrial motor control because the dual-core ARM Cortex-A9 HPS runs current/torque control loops at 800 MHz while the 110K logic elements implement deterministic PWM and encoder-capture hardware. The SX family's low static power suits always-on factory cabinets, and the industrial -40C to +100C temperature grade handles unconditioned control panels. Designers typically use the HPS EMAC for PROFINET/EtherCAT slave stacks and reserve FPGA fabric for high-speed field-oriented control loops with sub-microsecond latency.
Recommended
Video Surveillance and Machine Vision
The 5CSXFC6C6U23I7N suits video surveillance because the FPGA fabric can ingest MIPI CSI-2 or parallel camera data through soft IP while the Cortex-A9 cores run OpenCV-based analytics, H.264 encoding, and network streaming. 110K logic elements are enough for 1080p60 pipelines plus on-chip frame buffers, and the HPS DDR3 controller with ECC prevents single-event upsets in unattended deployments. Power dissipation stays below 6 W for fanless IP-camera enclosures.
Recommended
Automotive Infotainment Head Unit
The 5CSXFC6C6U23I7N fits automotive infotainment because the HPS runs Android Automotive OS or QNX for HMI graphics while the FPGA fabric drives LVDS display panels and MOST or CAN-FD automotive networks. The I7 industrial temperature grade is suitable for cabin environments; for under-hood or ADAS applications migrate to the A7 automotive variant 5CSXFC6C6U23A7N. Designers leverage the FPGA for pixel-perfect rendering pipelines offloading the Cortex-A9 cores.
Recommended
Industrial Ethernet Protocol Bridge
The 5CSXFC6C6U23I7N bridges PROFINET, EtherCAT, EtherNet/IP, and legacy RS-485 fieldbuses because the HPS runs the TCP/IP and real-time Ethernet stacks while the FPGA fabric implements deterministic cut-through forwarding in hardware. 110K logic elements hold several soft MAC cores simultaneously, and the HPS EMAC plus USB 2.0 OTG simplify gateway configuration. Industrial temperature grade and lead-free packaging meet factory-floor reliability requirements.
Recommended
Edge AI Inference Gateway
The 5CSXFC6C6U23I7N runs lightweight AI inference at the edge because the dual-core ARM Cortex-A9 HPS executes TensorFlow Lite or ONNX models while FPGA logic accelerates quantized CNN kernels via variable-precision DSP blocks. With 110K LE and embedded M10K memory blocks, the part delivers 1-2 GOPS/W efficiency for predictive-maintenance and anomaly-detection workloads in industrial IoT. The HPS EMAC and CAN interfaces connect directly to PLCs and SCADA systems.
Recommended
Medical Diagnostic Imaging
The 5CSXFC6C6U23I7N fits medical diagnostic imaging because the FPGA fabric pre-processes high-bandwidth ultrasound or endoscopy data streams in real time while the Cortex-A9 cores manage the user interface, DICOM storage, and network connectivity. 110K logic elements support mid-resolution beamforming and noise-reduction pipelines, and the DDR3 controller with ECC preserves image integrity. Industrial temperature grade and lead-free packaging suit clinical environments; for IEC 60601-1 compliance, add appropriate isolation around the SoC.
Recommended
Aerospace Avionics Subsystem
The 5CSXFC6C6U23I7N serves aerospace avionics subsystems where FPGA fabric delivers deterministic ARINC 429 or MIL-STD-1553 bus handling and the Cortex-A9 HPS runs flight-management software. The SX family's low static power suits unpressurized avionics bays, and the industrial temperature grade handles thermal cycling at altitude. Pair the SoC with a companion watchdog supervisor and conformal-coated PCB for DO-254 design-assurance workflows.
Recommended
Recommended Products Summary
Engineering reference data for 5CSXFC6C6U23I7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5CSXFC6C6U23I7LN | 5CSXFC6C6U23C8N | 5CSXFC6C6U23C7N | 5CSXFC6C6U23C6N | 5CSXFC5C6U23I7N |
|---|---|---|---|---|---|---|
| Package | 672-UBG-A (U23) | 672-UBG-A (U23) - same | 672-UBG-A (U23) - same | 672-UBG-A (U23) - same | 672-UBG-A (U23) - same | 672-UBG-A (U23) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 110,000 | 110,000 | 110,000 | 110,000 | 110,000 | 85,000 |
| HPS | Dual ARM Cortex-A9 @ 800 MHz | Dual ARM Cortex-A9 @ 800 MHz | Dual ARM Cortex-A9 @ 800 MHz | Dual ARM Cortex-A9 @ 800 MHz | Dual ARM Cortex-A9 @ 800 MHz | Dual ARM Cortex-A9 @ 800 MHz |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Speed Grade | 6 | 6 | 8 (faster) | 7 (faster) | 6 | 6 |
| Process / Core Voltage | 28 nm / 1.1 V | 28 nm / 1.1 V | 28 nm / 1.1 V | 28 nm / 1.1 V | 28 nm / 1.1 V | 28 nm / 1.1 V |
| Approx. Unit Price (USD, qty 1) | 480.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Largest 110K LE logic density in the SX family with same U23 package (vs 5CSXFC5C6U23I7N)
- Industrial temperature grade with no A7 premium required for many deployments (vs 5CSXFC6C6U23A7N)
- Same U23 BGA across temperature/speed migration paths (vs 5CSXFC6C6U23C8N)
Design Notes
The 672-UBG-A package uses 1.0 mm ball pitch on a 23 x 23 mm body. PCB stack-up must specify 0.4-0.5 mm microvia-in-pad fabrication, ENIG or ENEPIG surface finish, and 1 oz copper on outer layers. Allow at least 6 layers with two dedicated ground planes adjacent to the BGA to control return-current paths between HPS DDR3 and FPGA transceivers (when used in SX-stitched designs). Plan X-ray or endoscopic inspection for first-article builds because hidden solder balls cannot be visually inspected.
The Cyclone V SX SoC FPGA requires five separate power rails: VCCINT (1.1 V core), VCCPD (2.5 V/3.0 V configuration), VCCIO (1.2-3.3 V bank I/O), VCCRSTCLK (2.5 V), and a dedicated HPS rail set (VCC_HPS, VCC_HPS_IO, VCC_HPS_PLL) typically 1.1 V/1.5 V/2.5 V. Sequence the FPGA core rail before HPS power-on per the Cyclone V handbook to avoid latch-up; use a multi-rail PMIC such as the Intel Enpirion EM21xx family or equivalent TI TPS65xxx to guarantee monotonic startup. Estimated: total worst-case power is approximately 6-8 W for the C6 density at full HPS and fabric utilization.
At typical 3-5 W dissipation, the 672-UBG-A package can be cooled with a 15 x 15 mm copper pour on the top layer plus four thermal vias under the central die-attach pad. Estimated: with theta_JA around 18-22 C/W for the UBG-A, a 5 W load yields a 90-110 C junction temperature in still air, which is acceptable only at industrial grade with proper derating. For sealed enclosures, add a small 20 mm fan or attach a 30 x 30 mm aluminum heat spreader via 0.5 mm thermal pad.
HPS DDR3 traces must be length-matched to within 25 mil across byte lanes and routed on a single inner stripline layer referenced to a continuous ground plane. FPGA fabric LVDS or DDR3 interfaces should be routed with 100 ohm differential impedance and isolated from HPS signals by at least 4x the dielectric thickness (3W rule) to avoid crosstalk. Use the Intel Quartus Prime pin planner and the Cyclone V External Memory Interface Toolkit to verify timing margins before tape-out.
Three common pitfalls: (1) omitting the MSEL configuration mode pins, which default to a non-functional AS mode and brick the board; (2) failing to hold the HPS cold-reset line during FPGA configuration, which causes the Cortex-A9 cores to boot into an undefined state; (3) using an inadequate decoupling network (Intel recommends 0402-size 0.1 uF + 10 uF per power pin). Always reference the Cyclone V SoC FPGA Hardware Design Checklist before final schematic review.
Compliance Information
RoHS and lead-free per Intel product page. I7 industrial temperature grade is not AEC-Q100 qualified - for automotive use choose 5CSXFC6C6U23A7N. Halogen-free status not stated in available data and is marked unknown.
