BSD235CH6327XTSA1 - 20V Complementary N+P MOSFET | Infineon OptiMOS™
MPN: BSD235CH6327XTSA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.38 | $3.80 |
| 100 | $0.27 | $27.00 |
| 500 | $0.21 | $105.00 |
| 1,000 | $0.16 | $160.00 |
| 3,000 | $0.12 | $360.00 |
Drop-in alternatives for BSD235CH6327XTSA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
BSD235CH6327
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
BSD235CN6327
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BSD235C L6327
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BSH205G2R
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SI1553DL-T1-GE3
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DMC2700UDG-7
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BSD235CH6327XTSA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Part Family | OptiMOS™ |
| Configuration | N+P complementary dual MOSFET |
| Drain-to-Source Voltage (VDS) | 20 V |
| N-Channel Continuous Drain Current (ID) | 950 mA |
| P-Channel Continuous Drain Current (ID) | 530 mA (negative polarity) |
| Total Power Dissipation (Ptot) | 500 mW |
| Package Type | PG-SOT363-6-1 (SOT-363, 6-pin) |
| Mounting Type | Surface Mount |
| Technology | OptiMOS™ low-voltage |
| Operating Temperature Range | -55 °C to +150 °C (junction) |
| Polarity | N-channel + P-channel |
| Channel Mode | Enhancement |
| RoHS Status | Compliant (lead-free) |
| MSL Level | 1 |
| Pin Count | 6 |
BSD235CH6327XTSA1 Pin Configuration
| Pin 1 | S1 — Source of MOSFET 1 (typically n-channel) |
| Pin 2 | G1 — Gate of MOSFET 1 (typically n-channel) |
| Pin 3 | D2 — Drain of MOSFET 2 (typically p-channel) |
| Pin 4 | S2 — Source of MOSFET 2 (typically p-channel) |
| Pin 5 | G2 — Gate of MOSFET 2 (typically p-channel) |
| Pin 6 | D1 — Drain of MOSFET 1 (typically n-channel) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
BSD235CH6327XTSA1 is suitable for 6 applications: USB-PD Load Switch, Battery Protection / 1-Cell Li-ion Management, Half-Bridge / H-Bridge Motor Driver (small signal), Level Shifter / Logic Translator, Synchronous Rectifier Signal Stage, Relay / Solenoid Driver.
USB-PD Load Switch
The BSD235CH6327XTSA1 is well matched to USB-Power-Delivery (USB-PD) load switches because its 20 V VDS comfortably exceeds the 5 V / 9 V / 15 V / 20 V PD source voltages, the 950 mA n-channel ID handles 900 mA USB-3.0 inrush, and the p-channel section can act as a high-side 5 V switch. Used as a back-to-back N+P pair, it isolates the source from the sink until the PD contract is negotiated, preventing leakage from unselected sources. Place a 100 kΩ pull-down on the n-channel gate and a 100 kΩ pull-up on the p-channel gate to define a safe default-off state.
Recommended
Battery Protection / 1-Cell Li-ion Management
For 1-cell Li-ion battery management, the BSD235CH6327XTSA1 is used as the discharge / charge FET pair in a protection circuit where its 20 V VDS comfortably exceeds the 4.2 V max charge voltage. The 950 mA n-channel handles up to 2C discharge current, while the p-channel handles charging paths. The OptiMOS™ low-voltage process gives low VGS(th) (~1.0 V typical) which simplifies driving from a single-cell Li-ion logic level. Place a TVS such as SMAJ16A across the pack to clamp inductive transients during abnormal disconnect.
Recommended
Half-Bridge / H-Bridge Motor Driver (small signal)
For small DC motors (≤500 mA continuous) such as vibration motors, focus actuators, or miniature fans, the BSD235CH6327XTSA1 forms a compact half-bridge or full H-bridge when two devices are used. Its complementary polarity means each half-bridge needs only one part, saving PCB area over using two N-only arrays. The 20 V VDS supports up to 18 V motor rails, and the 500 mW dissipation budget is sufficient for short-duty-cycle motion control. Add 100 Ω gate resistors and a 10 kΩ gate-source pull-down/up to keep the half-bridge in a defined state during MCU reset.
Recommended
Level Shifter / Logic Translator
The BSD235CH6327XTSA1 is widely used as a discrete level-shifter pair: the n-channel implements a low-side reference translation, and the p-channel pulls the high-side rail up to a higher voltage (e.g., translating 1.8 V GPIO to 3.3 V or 5 V peripherals). The 20 V VDS accommodates 5 V, 3.3 V, and 1.8 V rails with margin. Low gate charge (Qg ~ 0.5 nC typical) means the translator can switch at 1 MHz+ with negligible dynamic loss. Use 10 Ω series gate resistors to dampen the LC ringing between the gate trace and the source/drain capacitances.
Recommended
Synchronous Rectifier Signal Stage
In a low-power DC-DC converter, the BSD235CH6327XTSA1 can serve as the low-side synchronous-rectifier signal driver — using the n-channel as the synchronous FET gate-drive buffer — in converters up to about 3 A. The 20 V VDS supports 12 V input rails with substantial margin, and the fast switching transitions of OptiMOS™ minimize dead-time. For higher currents, two BSD235C in parallel share conduction losses. Place a Schottky diode across the synchronous FET body-diode to reduce reverse-recovery loss and protect against duty-cycle overshoot.
Recommended
Relay / Solenoid Driver
For driving small 5 V or 12 V relays and solenoids, the BSD235CH6327XTSA1 is well suited: the n-channel acts as the low-side driver, the p-channel as the high-side return path, and the 950 mA / 530 mA currents handle most signal-relay coils. The 20 V VDS comfortably exceeds 12 V relay rail. Add a flyback diode (e.g., 1N4148) across the relay coil to absorb the inductive kick when the FET turns off. For 24 V industrial relays, choose a higher-VDS part (e.g., 30 V or 40 V OptiMOS™) instead.
Recommended
Recommended Products Summary
Engineering reference data for BSD235CH6327XTSA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | BSD235CH6327 | BSD235CN6327 | BSD235C L6327 | BSH205G2R | SI1553DL-T1-GE3 | DMC2700UDG-7 |
|---|---|---|---|---|---|---|---|
| Package | PG-SOT363-6-1 (SOT-363) | PG-SOT363-6-1 - same | PG-SOT363-6-1 - same | PG-SOT363-6-1 - same | SOT-363 - same | SOT-363 - same | SOT-363 - same |
| Brand | Infineon Technologies | Infineon Technologies - same | Infineon Technologies - same | Infineon Technologies - same | Infineon Technologies - same | Vishay Intertechnology | Diodes Incorporated |
| Polarity | N + P complementary | N + P complementary | N + P complementary | N + P complementary | Dual P-channel | N + P complementary | N + P complementary |
| VDS max | 20 V | 20 V | 20 V | 20 V | 20 V | 20 V | 20 V |
| N-channel ID continuous | 950 mA | 950 mA | 950 mA | 950 mA | N/A (P-channel only) | [DATA_NEEDED] | [DATA_NEEDED] |
| P-channel ID continuous | 530 mA | 530 mA | 530 mA | 530 mA | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Total Power Dissipation | 500 mW | 500 mW | 500 mW | 500 mW | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Technology | OptiMOS™ low-voltage | OptiMOS™ | OptiMOS™ | OptiMOS™ | OptiMOS™ | Siliconix TrenchFET | Diodes MOSFET |
Key Differentiators
- Complementary N+P in a single SOT-363 — saves one PCB footprint vs. two separate N-only or P-only dual arrays (vs SI1553DL-T1-GE3)
- OptiMOS™ low-voltage technology — Infineon's market-leading trench MOSFET process (vs DMC2700UDG-7)
- Wide operating junction temperature range -55 °C to +150 °C — industrial-grade qualification (vs BSH205G2R)
- AEC-qualified OptiMOS™ process — Infineon's automotive-grade silicon-on-chip technology (vs SI1553DL-T1-GE3)
Design Notes
The PG-SOT363-6-1 package has a typical θJA around 350 °C/W on a standard 1 oz JEDEC EIA/JESD51 2s2p test board. At total Ptot = 500 mW, the junction temperature rise above 25 °C ambient is roughly 175 °C, which exceeds the 150 °C Tj max. Practical guidance: keep total package dissipation below 250 mW (derate by 50 %) to maintain Tj ≤ 125 °C in continuous operation. Add thermal vias under the central SOT-363 pad and copper pours on both sides of the PCB if higher dissipation is needed.
Keep the gate-drive traces short (<5 mm) and route them away from the drain node to minimize the Cgd * dv/dt induced turn-on. A 10 Ω gate series resistor (Rgate) damps the LC resonance between gate-trace inductance and the FET's Ciss, without slowing switching significantly. Place a 100 kΩ gate-source resistor on each FET to keep the device in a defined off state during MCU reset or POR — important for half-bridge configurations where a single high-side turn-on without a low-side can cross-conduct.
Do not assume the BSD235CH6327XTSA1 pinout is the same as every SOT-363 dual MOSFET. The standard BSD235C layout (S1, G1, D2, S2, G2, D1) differs from some Vishay Siliconix parts (e.g., Si1553DL uses 1=D1, 2=G1, 3=S2, 4=G2, 5=D2, 6=S1). Always re-verify pinout against the datasheet before PCB swap. Exceeding the 20 V VDS rating — even transient — destroys the die; add a TVS such as SMAJ18CA across the drain-source of each FET for inductive-load protection.
Compliance Information
RoHS compliant per Infineon product page; OptiMOS™ is lead-free finish. Not AEC-Q100 qualified by default — confirm with Infineon automotive part number if automotive-grade is required.
