IPL60R065P7AUMA1 - 600V 65mΩ CoolMOS P7 MOSFET | Infineon
MPN: IPL60R065P7AUMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3.84 | $3.84 |
| 10 | $3.42 | $34.20 |
| 100 | $2.96 | $296.00 |
| 500 | $2.55 | $1,275.00 |
| 1,000 | $2.18 | $2,180.00 |
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View Datasheet →IPL60R065P7AUMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Technology Family | CoolMOS™ P7 (superjunction) |
| Drain-Source Voltage (V<sub>DS</sub>) | 600 V |
| Continuous Drain Current (I<sub>D</sub>, T<sub>C</sub>=25 °C) | 41 A |
| On-Resistance (R<sub>DS(on)</sub>, V<sub>GS</sub>=10 V) | 65 mΩ (max) |
| Power Dissipation (P<sub>D</sub>, T<sub>C</sub>=25 °C) | 201 W |
| Gate Threshold Voltage (V<sub>GS(th)</sub>) | 3.5 V |
| Input Capacitance (C<sub>iss</sub>, V<sub>DS</sub>=400 V) | 2895 pF |
| Rise Time (t<sub>r</sub>) | 7 ns |
| Fall Time (t<sub>f</sub>) | 4 ns |
| Operating Temperature Range | -55 °C to +150 °C (T<sub>j</sub>) |
| Package | PG-VSON-4 (surface mount with exposed pad) |
| Number of Pins | 4 |
| Mounting Type | Surface Mount |
| Channel Type | N-Channel |
| Polarity | Single N-channel |
| Drain to Source Voltage | 650 V (rating per AiEMA spec) |
| R<sub>DS(on)</sub> (max, V<sub>GS</sub>=10 V, T<sub>j</sub>=25 °C) | 0.053 Ω |
| RoHS Status | Compliant |
| MSL Level | 1 (per JEDEC J-STD-020) |
| Halogen-Free | Yes |
IPL60R065P7AUMA1 Pin Configuration
| Pin 1 | Source — Source connection (bonded to exposed pad) |
| Pin 2 | Source — Source connection (bonded to exposed pad) |
| Pin 3 | Source — Source connection (bonded to exposed pad) |
| Pin 4 | Gate — Gate drive input |
| Pin EP | Source (Exposed Pad) — Thermal pad, electrically bonded to Source; MUST be soldered to PCB copper pour for thermal dissipation |
Safe Operating Area (DC, T_C = 25 °C)
Typical Applications
IPL60R065P7AUMA1 is suitable for 6 applications: Switched-Mode Power Supplies (SMPS), Power Factor Correction (PFC) Boost Stages, Half-Bridge / Full-Bridge Converters, LLC Resonant Converters, Industrial Motor Drives, Telecom / Server Rectifiers.
Switched-Mode Power Supplies (SMPS)
IPL60R065P7AUMA1 fits SMPS primary-side switching with its 600 V V<sub>DS</sub> rating that handles rectified universal AC mains (85-305 VAC → ~400 V DC bus), 65 mΩ R<sub>DS(on)</sub> minimizing conduction loss, and CoolMOS P7 fast switching that improves efficiency across load. Placed as the main switch in flyback, forward, or half-bridge topologies, this part delivers the best-in-class figure-of-merit that P7 brings over older P6 generations. The PG-VSON-4 package keeps a compact power stage while exposing a large Source pad for thermal dissipation, supporting converter designs up to ~3 kW in continuous conduction.
Recommended
Power Factor Correction (PFC) Boost Stages
IPL60R065P7AUMA1 is well-suited to CCM PFC boost stages operating from a 400 V DC bus: its 600 V drain rating provides ample margin for line transients, the 65 mΩ R<sub>DS(on)</sub> keeps conduction loss manageable at high line (230 VAC), and the CoolMOS P7 platform's low reverse-recovery charge (Q<sub>rr</sub>) reduces switching loss in CCM hard-switched operation. Used between the bridge rectifier and the DC bus capacitor, this part enables >95% PFC stage efficiency. The exposed Source pad supports the continuous high-current conduction duty cycle of a boost PFC stage at full load.
Recommended
Half-Bridge / Full-Bridge Converters
IPL60R065P7AUMA1 works as primary-side switch in 600 V class half-bridge and full-bridge converters where two MOSFETs alternately switch at 100-200 kHz to drive a high-isolation transformer. The 65 mΩ R<sub>DS(on)</sub> trades off against the body-diode's reverse-recovery behavior, and the CoolMOS P7 family has been optimized for hard-switched bridge topologies. Compared to a planar MOSFET, the superjunction architecture cuts switching loss by 30-50% at the same R<sub>DS(on)</sub>, enabling higher switching frequencies and smaller magnetics in the converter design.
Recommended
LLC Resonant Converters
IPL60R065P7AUMA1 serves as the primary switch in LLC resonant converter topologies for high-density server and telecom power supplies. In LLC, MOSFET switching losses are dominated by turn-off loss rather than turn-on (zero-voltage switching on the primary side), and the CoolMOS P7 low Q<sub>g</sub> and fast fall time (4 ns) minimize turn-off loss. Its 65 mΩ R<sub>DS(on)</sub> handles the resonant tank current well, and the 600 V V<sub>DS</sub> rating comfortably covers the rectified-mains DC bus plus resonant overshoot.
Recommended
Industrial Motor Drives
IPL60R065P7AUMA1 fits the DC bus switching stage of low-voltage industrial motor drives (3-phase inverters for sub-500 V DC bus systems) where 600 V-rated MOSFETs switch at 4-16 kHz to drive induction or BLDC motors. The 41 A continuous current rating handles motor phase currents up to ~30 A RMS, and the PG-VSON-4 package supports high-density power-stage layouts. CoolMOS P7's rugged body-diode tolerates the dead-time cross-conduction events typical of motor drive PWM, simplifying drive design.
Recommended
Telecom / Server Rectifiers
IPL60R065P7AUMA1 enables compact front-end rectifier stages for telecom (-48 V systems fed from AC mains) and server (380 V DC or HV-DC) power supplies, where 600 V MOSFETs switch at 65-100 kHz in CCM/DCM boundary-conduction modes. The CoolMOS P7 family offers improved ease-of-use with wider gate-drive compatibility (drives directly from 10-12 V PWM controllers without negative bias). With 65 mΩ R<sub>DS(on)</sub> and 41 A drain current, this part supports 1.5-3 kW rectifier designs in standard 1U/2U form factors.
Recommended
Recommended Products Summary
Engineering reference data for IPL60R065P7AUMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IPL60R065P7 | BSC098N10NS5ATMA1 | IPD60R600P7ATMA1 | IAUC100N04S6N028ATMA1 | BSC011N03LSATMA1 |
|---|---|---|---|---|---|---|
| Package | PG-VSON-4 (Source pin + exposed pad) | PG-VSON-4 - same | PG-VSON-8 (SuperSO8) - 8 pins | PG-VSON-4 - same VSON family | PG-VSON-8 (SuperSO8) | PG-VSON-8 (SuperSO8) |
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Drain-Source Voltage (V<sub>DS</sub>) | 600 V | 600 V | 100 V | 600 V | 40 V | 30 V |
| On-Resistance (R<sub>DS(on)</sub> max) | 65 mΩ | 65 mΩ | 9.8 mΩ | 600 mΩ | 2.8 mΩ | 1.1 mΩ |
| Continuous Drain Current (I<sub>D</sub>, T<sub>C</sub>=25 °C) | 41 A | 41 A | 50 A | 9 A | 100 A | 100 A |
| Technology Family | CoolMOS P7 (superjunction) | CoolMOS P7 (superjunction) | OptiMOS 5 (superjunction low-V) | CoolMOS P7 (superjunction) | OptiMOS 6 | OptiMOS 5 |
| Input Capacitance (C<sub>iss</sub>) | 2895 pF | 2895 pF | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Rise / Fall Time | 7 ns / 4 ns | 7 ns / 4 ns | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- CoolMOS P7 platform with improved ease-of-use over P6 (vs IPL60R065P6 (predecessor CoolMOS P6))
- Superjunction architecture - best-in-class figure-of-merit at 600 V (vs Planar 600 V MOSFETs (e.g., 2N60-series))
- Compact PG-VSON-4 with exposed Source pad (vs Through-hole TO-220 / TO-247)
Design Notes
Estimated: at P<sub>D</sub>=201 W with a typical PG-VSON-4 θ<sub>JA</sub> ~50 °C/W on a 50 mm² copper pour on JEDEC 1s0p test board, junction temperature rise is approximately 25 °C per watt of dissipation. Continuous full-load operation at 41 A drain current requires either (a) a larger copper area (>= 100 mm² to bring θ<sub>JA</sub> down to ~30 °C/W) or (b) forced-air cooling. Without thermal management, derate I<sub>D</sub> against T<sub>j</sub>=150 °C maximum.
Place the gate driver as close as possible to the Gate pin (pin 4) to minimize parasitic inductance in the gate loop. Use a 10 Ω gate resistor and a low-ESR ceramic bypass capacitor (100 nF minimum) on the gate-driver supply. The exposed Source pad MUST be soldered to a continuous copper pour that connects to all three Source pins (1, 2, 3) - split or missing Source pads create parasitic inductance and degrade switching performance.
Keep the power loop (input cap → drain → source → ground return) area as small as possible to minimize stray inductance L<sub>s</sub>, which causes V<sub>DS</sub> overshoot during turn-off and stresses the 600 V breakdown. For a half-bridge, use a low-inductance layout with the high-voltage bus capacitor directly adjacent to the MOSFETs. Estimate: a 20 nH stray inductance with 41 A turn-off (4 ns fall time) produces L<sub>s</sub>·di/dt overshoot of ~205 V - leaving only ~395 V of margin on a 400 V bus.
Do not exceed V<sub>GS</sub>=±20 V gate-source voltage (absolute maximum per superjunction MOSFET datasheets). Use a gate-source Zener clamp (typically 12-15 V) across Gate-Source to protect against V<sub>DS</sub> transients coupled through C<sub>gd</sub>. The 3.5 V V<sub>GS(th)</sub> means a UVLO'd gate driver can leave the MOSFET in linear mode, dissipating high power - design gate-driver UVLO threshold above 4-5 V minimum.
Compliance Information
Infineon industrial-grade CoolMOS P7 family. RoHS and REACH compliant per manufacturer datasheet. Halogen-free per Infineon environmental compliance. Not AEC-Q100 qualified - this is the industrial-grade variant; AEC-Q100 qualified automotive variants are in the same family but require explicit automotive part numbers.
