IQE036N08NM6CGATMA1 - 80V 118A OptiMOS 6 N-MOSFET | Infineon
MPN: IQE036N08NM6CGATMA1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.62 | $16.20 |
| 100 | $1.21 | $121.00 |
| 500 | $0.96 | $480.00 |
| 1,000 | $0.82 | $820.00 |
IQE036N08NM6CGATMA1 Overview
A power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch used to efficiently route or modulate current in power-conversion and motor-drive circuits. The OptiMOS 6 family sits at the high-current, low-Rds(on) tier of Infineon's trench-FET portfolio, positioned as a key building block inside the broader power-management hierarchy of synchronous DC-DC converters, hot-swap controllers, and e-fuse stages. The Source-Down PQFN package places the thermal pad on the source side rather than the drain, allowing direct top-side cooling and very low package parasitic inductance.
Key features of the IQE036N08NM6 include an industry-leading 3.6 mOhm maximum Rds(on) at 10 V Vgs, a logic-level friendly 1.0 V typical gate threshold, integrated ESD protection, and 100% Rg- and UIS-tested production. The Source-Down PG-TTFN-9-3 package reduces source inductance to under 1 nH and achieves a junction-to-case thermal resistance (RthJC) suitable for 125 W continuous dissipation when mounted on a properly sized copper land pattern with thermal vias to an internal plane.
Architecturally, the device uses Infineon's latest OptiMOS 6 trench cell, which shrinks pitch to single-digit microns and replaces the conventional drain-down lead frame with a copper-clip Source-Down structure. The result is a roughly 30% lower Rds(on) per area versus the previous OptiMOS 5 generation, plus reduced ringing during hard switching because the high-current source loop is on the top metal layer directly above the die.
Typical applications include 48 V server hot-swap and OR-ing FETs, telecom brick DC-DC converters, BLDC motor-drive half-bridges, battery protection FETs in power tools, and USB-PD/EPR high-current sink paths. The 80 V rating gives ample headroom above 48 V nominal buses and protects against transient spikes on 24 V industrial rails.
When designing with this part, pay close attention to PCB layout: the Source-Down package requires a flooded top-side copper pour stitched with thermal vias directly under the source pad. Always check safe operating area (SOA) curves before paralleling multiple devices for load sharing.
This page synthesizes distributor pricing, drop-in alternatives from the OptiMOS 6 family and competitor offerings, and practical layout/thermal notes not aggregated on a single manufacturer page.
Drop-in alternatives for IQE036N08NM6CGATMA1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IQE036N08NM6CGATMA1 (same form factor and footprint) — differing in Technology, Operating Temperature Range, Package, Drain-Source Voltage (VDS), Product Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IQE050N08NM5CGATMA1
✅ Drop-In✓ In Stock
$1.75 / Unit
View Datasheet →IQE036N08NM6CGSCATMA1
✅ Drop-In✓ In Stock
$0.88 / Unit
View Datasheet →IQE018N06NM6CGATMA1
✅ Drop-In✓ In Stock
$1.21 / Unit
View Datasheet →ISZ072N06NM6ATMA1
✅ Drop-In✓ In Stock
$0.38 / Unit
View Datasheet →BSC019N04LSGATMA1
✅ Drop-In📋 Reference alternative (not in catalog)
IQE036N08NM6CGATMA1 Maximum Ratings & Electrical Characteristics
| Manufacturer | Infineon Technologies |
| Product Family | OptiMOS 6 |
| Transistor Type | N-Channel MOSFET |
| Drain-Source Voltage (Vds) | 80 V |
| Continuous Drain Current (Id) at Tc | 118 A |
| Continuous Drain Current (Id) at Ta | 16.7 A |
| Rds(on) max at Vgs=10V | 3.6 mOhm |
| Gate Threshold Voltage (Vgs(th)) | 3.5 V (max) |
| Power Dissipation at Tc | 125 W |
| Power Dissipation at Ta | 2.5 W |
| Operating Temperature Range | -55 C to +175 C (junction, Tj) |
| Package | PG-TTFN-9-3 (Source-Down PQFN, 3.3 x 3.3 mm) |
| Mounting Type | Surface Mount |
| MSL Level | MSL1 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Technology | Trench MOSFET, OptiMOS 6 |
| Configuration | Single N-channel, Source-Down |
IQE036N08NM6CGATMA1 Pin Configuration
| Pin 1 | Source — Source terminal (top-side cooling pad, electrically common with pins 2-8) |
| Pin 2 | Source — Source terminal |
| Pin 3 | Source — Source terminal |
| Pin 4 | Source — Source terminal |
| Pin 5 | Source — Source terminal |
| Pin 6 | Source — Source terminal |
| Pin 7 | Source — Source terminal |
| Pin 8 | Source — Source terminal |
| Pin 9 | Gate — Gate drive input |
| Pin PAD | Drain — Drain terminal on bottom exposed pad |
Safe Operating Area (DC, Tj=175C)
Typical Applications
IQE036N08NM6CGATMA1 is suitable for 6 applications: 48 V Server Hot-Swap and OR-ing FET, Telecom Brick DC-DC Synchronous Rectifier, BLDC Motor Drive Half-Bridge, Battery Protection FET for Power Tools, USB-PD EPR High-Current Sink Path, Solar Optimizer / Bypass Switch.
48 V Server Hot-Swap and OR-ing FET
The IQE036N08NM6CGATMA1 is well suited for 48 V server hot-swap and OR-ing paths where the Source-Down PG-TTFN-9-3 package allows direct top-side cooling via a copper heat spreader or chassis rail. With 80 V Vds rating it survives 48 V nominal bus plus full transient avalanche envelope per the Infineon SOA curves, while 3.6 mOhm max Rds(on) at 10 V Vgs keeps conduction loss under 4 W at 30 A steady-state. The sub-1 nH source inductance minimizes ringing during hot-plug events, protecting upstream controllers. Place the part with a flooded top-side copper pour stitched with 9-12 thermal vias to an internal ground plane.
Recommended
Telecom Brick DC-DC Synchronous Rectifier
In isolated telecom brick DC-DC converters, the IQE036N08NM6CGATMA1 serves as the secondary-side synchronous rectifier MOSFET, replacing Schottky diodes to recover reverse-recovery losses. Its 80 V Vds rating comfortably covers 48 V input brick outputs after the main transformer, and the 3.6 mOhm Rds(on) reduces secondary-side conduction loss versus traditional diode-OR stages. The Source-Down package enables cold-plate attachment on the top side for high-density brick layouts. Use a dedicated low-side gate driver such as the 2ED21064S06JXUMA1 family and add 100 nF of local gate damping to suppress Miller-induced turn-on at high dV/dt.
Recommended
BLDC Motor Drive Half-Bridge
The IQE036N08NM6CGATMA1 is a strong candidate for BLDC motor-drive half-bridges in industrial pumps, fans, and e-bike controllers where the bus voltage sits at 24-60 V. The 80 V Vds rating absorbs motor back-EMF spikes during commutation, and the 118 A continuous Id rating supports peak torque transients without thermal throttling. The Source-Down PQFN-9 package has very low package inductance, reducing shoot-through risk in hard-switched half-bridges. Pair with a three-phase gate driver like the 6EDL04N02PRXUMA1 family and include 100 ns blanking time in firmware to prevent cross-conduction during complementary switching.
Recommended
Battery Protection FET for Power Tools
For 18-36 V cordless power tool battery packs, the IQE036N08NM6CGATMA1 acts as the high-side or low-side protection MOSFET between the cell stack and the tool's motor driver. Its 3.6 mOhm Rds(on) at full Vgs=10 V minimizes voltage drop during peak discharge, preserving tool runtime, while the 80 V Vds rating withstands inductive flyback from brushed or brushless motor windings. The Source-Down package lets the BMS PCB double as a heat spreader, and integrated ESD protection on the gate simplifies the cell-balancing interface. Use a dedicated battery monitor like the TLE9012QUXUMA1 to control the gate and implement over-current protection within 10 microseconds.
Recommended
USB-PD EPR High-Current Sink Path
In USB Power Delivery Extended Power Range (EPR) sink designs operating up to 48 V / 5 A, the IQE036N08NM6CGATMA1 functions as a load-switch FET on the VBUS path, providing inrush control and fault isolation. Its 80 V Vds rating gives substantial headroom above the 48 V EPR maximum, while 3.6 mOhm Rds(on) keeps the cable-end voltage drop below 100 mV at 5 A full load. The Source-Down PQFN-9 footprint allows PCB placement on the same thermal copper as the DC-DC converter, simplifying heat-sinking. Add a 10 kOhm gate pull-down to keep the path off during controller reset, and pair with a Type-C port controller like the TLD1125ELXUMA1.
Recommended
Solar Optimizer / Bypass Switch
The IQE036N08NM6CGATMA1 is suitable for photovoltaic optimizer and bypass-switch applications where each PV panel requires a low-loss switch capable of handling open-circuit voltage transients plus inductive kick from long string wiring. Its 80 V Vds rating is appropriate for short 60 V max strings, and the 3.6 mOhm Rds(on) minimizes annual energy yield loss compared to mechanical relays or higher-Rds MOSFETs. The Source-Down package allows top-side aluminum heat-spreader attachment in outdoor IP67 enclosures. Drive with an isolated gate driver such as the 2ED2106S06FXUMA1 and add a TVS diode across the source-drain to clamp lightning-induced transients.
Recommended
Recommended Products Summary
Engineering reference data for IQE036N08NM6CGATMA1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IQE050N08NM5CGATMA1 | IQE018N06NM6CGATMA1 | ISZ072N06NM6ATMA1 |
|---|---|---|---|---|
| Brand | Infineon Technologies | Infineon Technologies | Infineon Technologies | Infineon Technologies |
| Package | PG-TTFN-9-3 (PQFN 3.3x3.3 Source-Down) | PG-TTFN-9-3 (PQFN 3.3x3.3 Source-Down) - same | PG-TTFN-9-3 (PQFN 3.3x3.3 Source-Down) - same | PG-TTFN-9-3 (PQFN 3.3x3.3 Source-Down) - same |
| Drain-Source Voltage (Vds) | 80 V | 80 V | 60 V | 60 V |
| Rds(on) max at 10V Vgs | 3.6 mOhm | 5.0 mOhm | 1.8 mOhm | 7.2 mOhm |
| Generation | OptiMOS 6 | OptiMOS 5 | OptiMOS 6 | OptiMOS 6 |
| Package Type | Source-Down | Source-Down | Source-Down | Source-Down |
Key Differentiators
- Lower Rds(on) per area than OptiMOS 5 generation (vs IQE050N08NM5CGATMA1)
- Higher Vds rating than lower-Rds alternatives (vs IQE018N06NM6CGATMA1)
- Source-Down package enables top-side cooling (vs ISZ072N06NM6ATMA1)
Design Notes
Estimated layout guidance: The PG-TTFN-9-3 Source-Down package requires a flooded top-side copper pour on the source pad (pins 1-8), stitched with 9-12 thermal vias (0.3 mm drill, 1 mm pitch) directly to an internal ground plane. Do not place signal traces under the source pad. Estimated: with 2 oz copper top-side and a 4-layer 1 oz internal plane, the Source-Down configuration can achieve an effective RthJA near 35 C/W versus 50 C/W for a comparable drain-down QFN, halving the junction temperature rise at 30 A continuous load.
Estimated thermal calculation: at 30 A continuous drain current and 3.6 mOhm Rds(on), conduction loss is approximately 3.24 W (I^2 x R = 30^2 x 0.0036). With an effective RthJA of 35 C/W on a 2 oz top copper + 4-layer 1 oz internal plane stack-up, the junction temperature rise above ambient is approximately 113 C. At 25 C ambient the junction reaches 138 C, safely below the 175 C maximum. At 50 A continuous the loss rises to 9 W and junction temperature climbs above 175 C, requiring active cooling or a smaller Rds(on) part.
The Source-Down topology inverts the conventional QFN thermal path: heat flows from the die through the silicon substrate to the top-side source metal, then through the PCB copper. This allows direct attachment of a heat spreader or top-side cold plate, but requires that the top-side copper area be maximized and not covered with solder mask. Use a solder-mask-defined (SMD) pad for the source pins and a non-solder-mask-defined (NSMD) pad for the bottom drain pad to prevent tombstoning during reflow.
Do not exceed Vgs = +/-20 V (per datasheet absolute maximum) - use a gate-drive Zener clamp if the controller is powered from a higher rail. Do not parallel devices without independent gate resistors to suppress parasitic oscillation. Do not rely on the 80 V Vds rating for repetitive avalanche operation - check the repetitive avalanche energy (Ear) rating in the datasheet and derate by 50% for production margin.
The Source-Down package reduces source inductance to under 1 nH, which significantly reduces Vgs ringing during hard switching. To further suppress Miller-induced turn-on, add a 10 kOhm gate-source resistor and place a 100 nF local gate-drive bypass capacitor within 5 mm of the gate pin. For switching frequencies above 100 kHz, use a ferrite bead in series with the gate to dampen high-frequency gate-loop resonance.
Compliance Information
RoHS compliant per Infineon product page. Not AEC-Q100 qualified (industrial/consumer grade). MSL1 per JEDEC J-STD-020.
